Why openSUSE is not compiled with a SSE3 instructions using?

SSE3 was introduced 15+ years ago.
IMHO when all system will be compiled with a SSE3 enabled, we can benefit with a (modest) speed-up.
Of course, this will be a new requirement: nowdays it is SSE2 (SSE2 is a part of AMD64), new will be SSE3.
But nearly all processors that in use supports SSE3.

Next steps (supporting SSSE3 = supplemental SSE3, SSE4, AVX, …) will be very hard because of Phenom and Phenom II which limits supporting instructions but are too fast to throw these processors away.

Probably because SUSE’s largest customer (Walmart) has 1000’s of Phenom FX computers that will still be used for the next 8-10 years. Heck, Walmart has some old Microchannel computers in use. I know their Fax servers are on old 486 based NCR Microchannel PCs.

Ironically Walmart is still running SUSE 11 not 15 but are supposed to be migrating to SUSE 15. Walmart has 1000’s of apps that have to be tested under 15 to see if anything breaks with the new libraries - I know many have libc issues and Walmart ISD hates “C” and wants to convert everything to Java (the world’s least secure language and least efficient size and speed wise).

What’s strange is, when I look in ‘/proc/cpuinfo’ I see this – AMD FX™-4100 Quad-Core Processor – for each CPU core:

model name      : AMD FX(tm)-4100 Quad-Core Processor
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 cx16 sse4_1 sse4_2 popcnt aes xsave avx lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt fma4 nodeid_msr topoext perfctr_core perfctr_nb cpb hw_pstate ssbd ibpb vmmcall arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold

If I’m not mistaken, this means that, for this CPU, the Leap 15.1 kernel is supporting the following Intel “Streaming SIMD Extensions” (SSE):

  1. SSE
  2. SSE2
  3. SSSE3
  4. SSE4.1
  5. SSE4.2
  7. LZCNT – “abm” flag …
  8. SSE4a
  9. FMA4
  10. F16C – previously “CVT16” – “cx16” flag …
  11. AVX

[HR][/HR]But, I could be mistaken …

It’s not the processor capability, it’s the applications, AFAIK the tune flag used is ‘generic’. If a user wants something more specific it would need to be recompiled…