compile a verilog program

hi, I’m new in this forum so I need a little help.
I have installed a searched in opesuse site, verilog program.
My problem is the compilation of a program in Verilog.
Thanks for helping me!

Welcome!

What do you want to compile into what? You have a Verilog-file (ore more of them), what do you want to do exactly? What tools do you use?

I use the Icarus verilog simulator, I follow this installation guide about opensuse http://iverilog.wikia.com/wiki/Installation_Guide.

I have a program in my home directory
such as the follow(hello.v):

module hello_world ;

initial begin
  $display ("Hello World by Deepak");
  #10 $finish;
end

endmodule 

how compile and execute this file?

I tried it with the package from ‘http://download.opensuse.org/repositories/science/openSUSE_11.2/’ (you don’t need to fix anything as far as I can see. Just install the rpm).

iverilog SOURCEFILE

will generate the file “a.out” in your current directory. This one is executable.

The package supplies 3 binaries, each having it’s own manpage. So, try

man iverilog
man iverilog-vpi
man vvp

for the options. I would also search for documentation on the Icarus project page: Icarus Verilog

Just to make sure:

  • http://download.opensuse.org/repositories/science/openSUSE_11.2/’ of course is a repository. You can use the one-click-install you can search for at Software.openSUSE.org. You don’t need to follow any installation-instructions from the Icarus-Website. But, you should uninstall your installed version if you want to use this.
  • You always speak about programs: Verilog is not a programming language, it is a hardware-description-language. If you want to develop hardware, you are fine, but if you want to develop programs, look for another language.

thanks for your answers.
Maybe I wanted to learn many
things very quickly, for this I asked general things,
fortunately I found a very nice Verilog tutorial
so I started from the beginning!