CPU: AMD Phenom II x6 1100T
mobo: Gigabyte GA-990FXA-UD5 (AMD 990FX/SB950 chipset)
Searches related to enabling the AMD-Vi say that it has to be enabled in the BIOS or (I believe it should be AND) have an IVRS table in the ACPI tables. However the kernel ring buffer reported by “dmesg” shows the following:
0.000000] ACPI: IVRS 00000000bfde0930 000F8 (v01 AMD RD890S 00202031 AMD 00000000)
...
0.000000] No AGP bridge found
0.000000] Node 0: aperture @ b0000000 size 32 MB
0.000000] Aperture pointing to e820 RAM. Ignoring.
0.000000] Your BIOS doesn't leave a aperture memory hole
0.000000] Please enable the IOMMU option in the BIOS setup
0.000000] This costs you 64 MB of RAM
0.000000] Mapping aperture over 65536 KB of RAM @ b4000000
and
0.772264] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40
0.832267] AMD-Vi: Lazy IO/TLB flushing enabled
0.832270] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
0.832272] Placing 64MB software IO TLB between ffff8800bbda0000 - ffff8800bfda0000
0.832274] software IO TLB at phys 0xbbda0000 - 0xbfda0000
So it looks like the AMD-Vi IOMMU has been enabled, and it looks like there’s an IVRS table. But it also looks like there have been 2 64MB tables created, but neither are for the AMD-Vi IOMMU. One appears to be for the GART and the other appears to be for the SWIOTLB mechansim.
What I don’t see (but I expected to see) is a 64MB area allocated for IOTLB entries.
Is there any way to test or confirm which IOMMU mechanism is actually being used by a running kernel?
Thanks,
ron